vhdl program
VHSIC Hardware Description Language A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. Initially conceived as a documentation language only, most of the language can today be used for simulation and logic synthesis. VHDL became the IEEE 1076 standard in 1987
- VHDL is a powerful and versatile language and offers numerous advantages
- Technology Independence: VHDL is independent of any specific technology or process. However, VHDL code can be written and then targeted for many different technologies
- Wide Range of Descriptions: VHDL can model hardware at various levels of design abstraction. VHDL can describe hardware from the standpoint of a "black box" to the gate level. VHDL also allows for different abstraction-level descriptions of the same component and allows the designer to mix behavioral descriptions with gate level descriptions
- Standard Language: The use of a standard language allows for easier documentation and the ability to run the same code in a variety of environments. Additionally, communication among designers and among design tools is enhanced by a standard language
- Design Management: Use of VHDL constructs, such as packages and libraries, allows common elements to be shared among members of a design group
- Flexible Design: VHDL can be used to model digital hardware as well as many other types of systems, including analog devices
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